An SiC semiconductor is a semiconductor made of SiC (silicon carbide) being a compound of carbon (C) and silicon (Si). The greatest feature of the SiC semiconductor is its physical properties suitable as a material of a semiconductor device (power device) to be used for power electronics. For example, in the case of 4H-SiC being commercially-available single crystal, the bandgap is 3.26 eV that is three times as wide as that of an Si semiconductor, the dielectric breakdown electric field strength is 2.8 MV/cm that is 10 times as high as that of an Si semiconductor, and the thermal conductivity is 4.9 W/cm that is three times as high as that of an Si semiconductor.
The SiC semiconductor is thermally and radiologically more stable than an Si semiconductor, and is excellent in terms of heat resistance, chemical resistance, and radiation resistance.
From these features, a MOS type field effect transistor (MOSFET) or a shot key barrier diode (SBD) made of an SiC semiconductor is preferably used for a power device to be used for power electronics, and an SiC semiconductor can be reduced in energy loss as compared with an Si semiconductor, so that this is considered to be important as a measure for energy saving.
However, in the MOSFET made of SiC, it has been conventionally regarded as a problem that there are a lot of defects in the interface between the gate insulating film (gate oxide film) and SiC, which makes the carrier mobility of the SiC small. With regard to this problem, an improvement in carrier mobility by reducing interface defects by devising the method for forming the gate insulating film by thermal oxidation method, CVD method, or interface nitridation method, etc., has been studied.
On the other hand, regarding the above-described problem, there is a technique for improving the carrier mobility by focusing on the crystal plane of SiC. In hexagonal SiC, an improvement in channel mobility by using a {03-38} plane which is known as a crystal plane with high carrier mobility as the interface between the gate insulating film and SiC is one of such methods.
Here, the {03-38} plane is a crystal plane tilted at 54.7 degrees in a <1-100> direction from a {0001} plane (refer to FIG. 1). The {03-38} plane of SiC corresponds to the {100} plane of Si, and is expected to have low interface state density and high carrier mobility.
However, conventionally, there has been a problem in which substrate formation using the {03-38} plane of SiC is difficult. The {03-38} plane can be cut only from a SiC single crystal mass, and if wafers with the {03-38} planes are obtained by cutting from a single crystal mass for circular wafers with the {0001} planes, the cut wafers are oval and the number of wafers to be obtained is limited (refer to FIG. 2).
In particular, it was very difficult to form the {03-38} plane on a trench sidewall in a vertical type device structure like a trench type MOSFET, etc.
As a technique for forming the {03-38} plane on trench sidewalls, for example, a technique with which trench sidewalls are formed into the {03-38} planes by forming a trench perpendicularly on a substrate using a {11-20} plane by plasma etching has already been known (Patent Document 1). With the technique disclosed in Patent Document 1, trench sidewalls are formed into the {03-38} planes by forming a trench perpendicularly on a substrate using the {11-20} plane by plasma etching (refer to FIG. 3), and the substrate surface is etched by approximately several nm to 0.1 μm by supplying hydrogen, etc., inside a reaction furnace under reduced pressure at 1500° C. or higher. Accordingly, a damaged layer after plasma etching for forming the trench is removed.
However, the technique disclosed in Patent Document 1 described above is disadvantageous in that the {11-20} plane itself to be used as a substrate is not commercially available and is difficult to obtain.
On the other hand, a technique with which uneven sub-trenches are intentionally formed on the bottom surface of a trench formed on a semiconductor substrate not by plasma etching but by dry etching treatment in a mixed atmosphere of chlorine and oxygen is known (Patent Document 2). According to the technique of Patent Document 1, by forming uneven sub-trenches on the trench bottom surface (refer to FIG. 4), a uniform CVD oxide film is formed inside the trench to improve the inter-element breakdown voltage.    [Patent Document 1] JPA-2006-351744    [Patent Document 2] JPA-2008-258265